1. Field of the Invention
The present invention relates to a CML (current mode logic) circuit and a clock distribution circuit utilizing the CML circuit.
2. Description of the Related Art
High speed serial transmission (including SerDes {serialization/deserialization}) requires a high-frequency clock. The jitter generated during the clock distribution, which adversely affects the transmission error rate, must be reduced. Therefore, in recent years CML circuits made up of MOS (Metal Oxide Semiconductors) are being utilized as clock drivers. They are capable of high-speed operation at a small amplitude and resistant to the effects of power supply noise.
CML circuits using MOS can be fabricated with the same process as other MOS circuits. That gives advantage in terms of layout to the CML circuits using MOS. However, CML circuits when made up of MOS possess low gain and large capacitance compared to bipolar circuits. So, if utilized as a clock driver, a large amplitude signal must be input to the input terminal of each clock driver stage in order to maintain amplitude of clocks sent to each circuit or device.
The output impedance of the CML circuit used as the clock driver must therefore be lowered and the drive power must be boosted when driving circuits or devices connected by long-distance wiring at a high-speed clock frequency. However a fixed current flows constantly in the CML circuit regardless of whether it is operating or not, so lowering the output impedance causes the problem that power consumption drastically increases.
In recent years, power supply voltages of circuits and threshold voltages (Vth) of transistors have dropped because MOS oxide films have become thinner and circuits have become minuter with higher circuit densities. The drop causes increasingly adverse effects when maximum device ratings cannot be met. The adverse effects, as described in the patent documents below, result in severe problems such as faulty logic circuit operation due to ringing, and deterioration or destruction of the MOS due to overshoot or undershoot. The ringing in the clock waveform that occurs due to excessive drive power must therefore be reduced.
[Patent document 1] Japanese Unexamined Patent Publication No. 2002-368600
[Patent document 2] Japanese Unexamined Patent Publication No. 2004-096750
Moreover, in clock drivers made up of CML circuits used for high-frequency (RF) clock distribution, failure of the first period clock wave to form due to effects of the RC components in clock wiring or the next stage of the clock driver must be prevented. Such failure occurs when resuming clock operation from a stopped clock state such as when turning on the power or clock gating. Also the power supply noise and power consumption during normal operation and low speed test operation must be reduced.